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<reviews count="16">
      <review id="108594">
      <media id="775013">
                                                        <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="2031">
                <term>Applications</term>
                <categorycode>I.6.3</categorycode>
              </ccs>
                          <ccs id="290">
                <term>High-Level Language Architectures</term>
                <categorycode>C.1.3</categorycode>
              </ccs>
                          <ccs id="73">
                <term>Verification</term>
                <categorycode>B.2.2</categorycode>
              </ccs>
                              </ccs_terms>
        <media_citation>
          <citation_details><authors><author id="2043982"><firstname><![CDATA[Virgil]]></firstname><lastname><![CDATA[Gligor]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>1</displayorder></author></authors><citation type="Article"><title><![CDATA[The verification of the protection mechanisms of high-level language machines]]></title><subtitle><![CDATA[]]></subtitle><published>1983-08-01 00:00:00.0</published><start_page>211</start_page><end_page>246</end_page><sponsoredby><![CDATA[4]]></sponsoredby><issueseries><![CDATA[4]]></issueseries><volume>12</volume><start_date>1983-08-01 00:00:00.0</start_date><end_date>1983-08-01 00:00:00.0</end_date><journal_title><![CDATA[International Journal of Parallel Programming]]></journal_title><journal_start_date>1989-02-01 00:00:00.0</journal_start_date><journal_end_date></journal_end_date><journal_id>5788</journal_id></citation></citation_details>        </media_citation>
        <fulltext>
                  </fulltext>
      </media>
      <review_dateofpub>01-FEB-85</review_dateofpub>
      <computingreviews_number></computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[This paper discusses a methodology for the (informal) verification of processor-supported protection mechanisms of high-level language architectures (e.g., INTEL iAPX 432).  The methodology takes an abstract model representation of the real hardware architecture and proceeds to show that protection constraints for the model are complete and correct.  Completeness and correctness are satisfied by]]></review_text>
      <review_link><![CDATA[http://www.reviews.com/review/review_review.cfm?review_id=108594]]></review_link>
      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="107410">
            <reviewer_name><![CDATA[Karl Nyberg]]></reviewer_name>
            <reviewer_institution><![CDATA[Verdix Corporation]]></reviewer_institution>
            <reviewer_location><![CDATA[Chantilly]]></reviewer_location>
            <reviewer_country><![CDATA[United States]]></reviewer_country>
            <reviewer_url><![CDATA[]]></reviewer_url>
            <review_count>2</review_count>
            <displayorder>1</displayorder>
          </reviewer>
              </reviewers>
    </review>
      <review id="109806">
      <media id="776990">
                              <media_isbn>0387119787</media_isbn>
                                                <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="1535">
                <term>Content Analysis And Indexing</term>
                <categorycode>H.3.1</categorycode>
              </ccs>
                          <ccs id="3164">
                <term>Distance Learning</term>
                <categorycode>K.3.1</categorycode>
              </ccs>
                          <ccs id="1538">
                <term>Indexing Methods</term>
                <categorycode>H.3.1</categorycode>
              </ccs>
                          <ccs id="1547">
                <term>Information Search And Retrieval</term>
                <categorycode>H.3.3</categorycode>
              </ccs>
                          <ccs id="2033">
                <term>Model Validation And Analysis</term>
                <categorycode>I.6.4</categorycode>
              </ccs>
                          <ccs id="1321">
                <term>Probabilistic Algorithms (Including Monte Carlo)</term>
                <categorycode>G.3</categorycode>
              </ccs>
                          <ccs id="1315">
                <term>Probability And Statistics</term>
                <categorycode>G.3</categorycode>
              </ccs>
                              </ccs_terms>
        <media_citation>
          <citation_details><authors><author id="2107883"><firstname><![CDATA[Jean]]></firstname><lastname><![CDATA[Tague]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>1</displayorder></author><author id="2041750"><firstname><![CDATA[Michael]]></firstname><lastname><![CDATA[Nelson]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>2</displayorder></author></authors><citation type="Proceedings"><title><![CDATA[Simulation of bibliographic retrieval databases using hyperterms]]></title><subtitle><![CDATA[]]></subtitle><published>1983-01-01 00:00:00.0</published><start_page></start_page><end_page></end_page><sponsoredby><![CDATA[]]></sponsoredby><journal_title><![CDATA[]]></journal_title><location><![CDATA[]]></location></citation></citation_details>        </media_citation>
        <fulltext>
                  </fulltext>
      </media>
      <review_dateofpub>01-SEP-85</review_dateofpub>
      <computingreviews_number></computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[This paper extends previous methods of validating probabilistic models of bibliographic retrieval systems. The authors found that for small (400-500 document) collections, models based on distributions involving second order dependencies among document and query terms provided a good fit. For larger collections, such distributions underestimated the probability of recurring sets of more than two]]></review_text>
      <review_link><![CDATA[http://www.reviews.com/review/review_review.cfm?review_id=109806]]></review_link>
      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="107770">
            <reviewer_name><![CDATA[L. Swanson]]></reviewer_name>
            <reviewer_institution><![CDATA[Educational Testing Service]]></reviewer_institution>
            <reviewer_location><![CDATA[Princeton]]></reviewer_location>
            <reviewer_country><![CDATA[United States]]></reviewer_country>
            <reviewer_url><![CDATA[]]></reviewer_url>
            <review_count>26</review_count>
            <displayorder>1</displayorder>
          </reviewer>
              </reviewers>
    </review>
      <review id="109807">
      <media id="776991">
                                                        <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="1393">
                <term>Data Models</term>
                <categorycode>H.2.1</categorycode>
              </ccs>
                          <ccs id="1472">
                <term>SQL</term>
                <categorycode>H.2.3</categorycode>
              </ccs>
                              </ccs_terms>
        <media_citation>
          <citation_details><authors><author id="1936527"><firstname><![CDATA[J.]]></firstname><lastname><![CDATA[Bradley]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>1</displayorder></author></authors><citation type="Article"><title><![CDATA[Application of SQL/N to the attribute-relation associations implicit in functional dependencies]]></title><subtitle><![CDATA[]]></subtitle><published>1983-04-01 00:00:00.0</published><start_page>65</start_page><end_page>86</end_page><sponsoredby><![CDATA[2]]></sponsoredby><issueseries><![CDATA[2]]></issueseries><volume>12</volume><start_date>1983-04-01 00:00:00.0</start_date><end_date>1983-04-01 00:00:00.0</end_date><journal_title><![CDATA[International Journal of Parallel Programming]]></journal_title><journal_start_date>1989-02-01 00:00:00.0</journal_start_date><journal_end_date></journal_end_date><journal_id>5788</journal_id></citation></citation_details>        </media_citation>
        <fulltext>
                  </fulltext>
      </media>
      <review_dateofpub>01-SEP-85</review_dateofpub>
      <computingreviews_number></computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[This paper describes a query language called SQL/N, an extension of SQL. The extension allow references to and quantification of subsets of relations based on natural associations between tuples in the same or distinct relations, without having to explicitly form these subsets using nested queries, as in ordinary SQL. The resulting SQL/N expressions are often simpler or appear more natural than]]></review_text>
      <review_link><![CDATA[http://www.reviews.com/review/review_review.cfm?review_id=109807]]></review_link>
      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="107814">
            <reviewer_name><![CDATA[F. Manola]]></reviewer_name>
            <reviewer_institution><![CDATA[Computer Corp. of America]]></reviewer_institution>
            <reviewer_location><![CDATA[Cambridge]]></reviewer_location>
            <reviewer_country><![CDATA[United States]]></reviewer_country>
            <reviewer_url><![CDATA[]]></reviewer_url>
            <review_count>7</review_count>
            <displayorder>1</displayorder>
          </reviewer>
              </reviewers>
    </review>
      <review id="130466">
      <media id="1646657">
                                                        <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="936">
                <term>Compilers</term>
                <categorycode>D.3.4</categorycode>
              </ccs>
                          <ccs id="948">
                <term>Optimization</term>
                <categorycode>D.3.4</categorycode>
              </ccs>
                          <ccs id="2948">
                <term>Parallel Architectures</term>
                <categorycode>C.1.4</categorycode>
              </ccs>
                          <ccs id="931">
                <term>Processors</term>
                <categorycode>D.3.4</categorycode>
              </ccs>
                          <ccs id="2944">
                <term>RISC/CISC, VLIW Architectures</term>
                <categorycode>C.1.1</categorycode>
              </ccs>
                          <ccs id="234">
                <term>Single Data Stream Architectures</term>
                <categorycode>C.1.1</categorycode>
              </ccs>
                              </ccs_terms>
        <media_citation>
          <citation_details><authors><author id="2145964"><firstname><![CDATA[Han]]></firstname><lastname><![CDATA[Yun]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>1</displayorder></author><author id="1887774"><firstname><![CDATA[Jihong]]></firstname><lastname><![CDATA[Kim]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>2</displayorder></author><author id="1829475"><firstname><![CDATA[Soo]]></firstname><lastname><![CDATA[Moon]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>3</displayorder></author></authors><citation type="Article"><title><![CDATA[Time optimal software pipelining of loops with control flows]]></title><subtitle><![CDATA[]]></subtitle><published>2003-10-01 00:00:00.0</published><start_page>339</start_page><end_page>391</end_page><sponsoredby><![CDATA[5]]></sponsoredby><issueseries><![CDATA[]]></issueseries><volume>31</volume><start_date>2003-10-01 00:00:00.0</start_date><end_date>2003-10-01 00:00:00.0</end_date><journal_title><![CDATA[International Journal of Parallel Programming]]></journal_title><journal_start_date>1989-02-01 00:00:00.0</journal_start_date><journal_end_date></journal_end_date><journal_id>5788</journal_id></citation></citation_details>        </media_citation>
        <fulltext>
                      <link>
              <url><![CDATA[http://dx.doi.org/10.1023/A:1027387028481]]></url>
              <type><![CDATA[DOI]]></type>
              <source><![CDATA[KLUWER]]></source>
            </link>
                  </fulltext>
      </media>
      <review_dateofpub>26-NOV-04</review_dateofpub>
      <computingreviews_number>0505-0588</computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[This paper is in the area of compiler optimizations for processors, such as very long instruction word (VLIW) and super scalar, processors which exploit instruction-level parallelism. A well-known technique is software pipelining of loops in the input programs. The paper presents a solution for the problem of software pipelining of loops with control flows in the loop bodies.
The first section]]></review_text>
      <review_link><![CDATA[http://www.reviews.com/review/review_review.cfm?review_id=130466]]></review_link>
      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="122586">
            <reviewer_name><![CDATA[Maulik A. Dave]]></reviewer_name>
            <reviewer_institution><![CDATA[Self]]></reviewer_institution>
            <reviewer_location><![CDATA[Dunwoody]]></reviewer_location>
            <reviewer_country><![CDATA[United States]]></reviewer_country>
            <reviewer_url><![CDATA[http://mdave.atspace.com]]></reviewer_url>
            <review_count>51</review_count>
            <displayorder>1</displayorder>
          </reviewer>
              </reviewers>
    </review>
      <review id="130298">
      <media id="1646661">
                                                        <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="84">
                <term>Design Styles</term>
                <categorycode>B.3.2</categorycode>
              </ccs>
                          <ccs id="3066">
                <term>Parallel And Vector Implementations</term>
                <categorycode>G.4</categorycode>
              </ccs>
                          <ccs id="2948">
                <term>Parallel Architectures</term>
                <categorycode>C.1.4</categorycode>
              </ccs>
                          <ccs id="2941">
                <term>Performance Analysis And Design Aids</term>
                <categorycode>B.8.2</categorycode>
              </ccs>
                          <ccs id="381">
                <term>Performance Of Systems</term>
                <categorycode>C.4</categorycode>
              </ccs>
                          <ccs id="93">
                <term>Shared Memory</term>
                <categorycode>B.3.2</categorycode>
              </ccs>
                              </ccs_terms>
        <media_citation>
          <citation_details><authors><author id="1910768"><firstname><![CDATA[Daisuke]]></firstname><lastname><![CDATA[Takahashi]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>1</displayorder></author><author id="1836413"><firstname><![CDATA[Mitsuhisa]]></firstname><lastname><![CDATA[Sato]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>2</displayorder></author><author id="1738595"><firstname><![CDATA[Taisuke]]></firstname><lastname><![CDATA[Boku]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>3</displayorder></author></authors><citation type="Article"><title><![CDATA[Performance evaluation of the Hitachi SR8000 using SPEC OMP2001 benchmarks]]></title><subtitle><![CDATA[]]></subtitle><published>2003-06-01 00:00:00.0</published><start_page>185</start_page><end_page>196</end_page><sponsoredby><![CDATA[3]]></sponsoredby><issueseries><![CDATA[]]></issueseries><volume>31</volume><start_date>2003-06-01 00:00:00.0</start_date><end_date>2003-06-01 00:00:00.0</end_date><journal_title><![CDATA[International Journal of Parallel Programming]]></journal_title><journal_start_date>1989-02-01 00:00:00.0</journal_start_date><journal_end_date></journal_end_date><journal_id>5788</journal_id></citation></citation_details>        </media_citation>
        <fulltext>
                      <link>
              <url><![CDATA[http://dx.doi.org/10.1023/A:1023034601563]]></url>
              <type><![CDATA[URL]]></type>
              <source><![CDATA[]]></source>
            </link>
                  </fulltext>
      </media>
      <review_dateofpub>19-OCT-04</review_dateofpub>
      <computingreviews_number></computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[This paper compares the performance of an eight-way symmetric multiprocessor (SMP), developed by Hitachi, with a Hewlett Packard (HP) and Silicon Graphics (SGI) SMP using the OpenMP version of SPEC2001. The Hitachi system provides a hardware mechanism for handling barriers, and takes advantage of the pseudo-vector processing (PVP) feature of the PowerPC processors. PVP supports the pipelining of]]></review_text>
      <review_link><![CDATA[http://www.reviews.com/review/review_review.cfm?review_id=130298]]></review_link>
      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="115870">
            <reviewer_name><![CDATA[Farnaz Toussi]]></reviewer_name>
            <reviewer_institution><![CDATA[IBM Corporation]]></reviewer_institution>
            <reviewer_location><![CDATA[Rochester]]></reviewer_location>
            <reviewer_country><![CDATA[United States]]></reviewer_country>
            <reviewer_url><![CDATA[]]></reviewer_url>
            <review_count>16</review_count>
            <displayorder>1</displayorder>
          </reviewer>
              </reviewers>
    </review>
      <review id="130094">
      <media id="1647050">
                                                        <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="1046">
                <term>Distributed Systems</term>
                <categorycode>D.4.7</categorycode>
              </ccs>
                          <ccs id="948">
                <term>Optimization</term>
                <categorycode>D.3.4</categorycode>
              </ccs>
                          <ccs id="1042">
                <term>Organization And Design</term>
                <categorycode>D.4.7</categorycode>
              </ccs>
                          <ccs id="1054">
                <term>Performance</term>
                <categorycode>D.4.8</categorycode>
              </ccs>
                          <ccs id="931">
                <term>Processors</term>
                <categorycode>D.3.4</categorycode>
              </ccs>
                          <ccs id="93">
                <term>Shared Memory</term>
                <categorycode>B.3.2</categorycode>
              </ccs>
                              </ccs_terms>
        <media_citation>
          <citation_details><authors><author id="2478392"><firstname><![CDATA[N]]></firstname><lastname><![CDATA[Manoj]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>1</displayorder></author><author id="2255729"><firstname><![CDATA[K]]></firstname><lastname><![CDATA[Manjunath]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>2</displayorder></author><author id="1723325"><firstname><![CDATA[R.]]></firstname><lastname><![CDATA[Govindarajan]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>3</displayorder></author></authors><citation type="Article"><title><![CDATA[CAS-DSM]]></title><subtitle><![CDATA[a compiler assisted software distributed shared memory]]></subtitle><published>2004-04-01 00:00:00.0</published><start_page>77</start_page><end_page>122</end_page><sponsoredby><![CDATA[2]]></sponsoredby><issueseries><![CDATA[]]></issueseries><volume>32</volume><start_date>2004-04-01 00:00:00.0</start_date><end_date>2004-04-01 00:00:00.0</end_date><journal_title><![CDATA[International Journal of Parallel Programming]]></journal_title><journal_start_date>1989-02-01 00:00:00.0</journal_start_date><journal_end_date></journal_end_date><journal_id>5788</journal_id></citation></citation_details>        </media_citation>
        <fulltext>
                      <link>
              <url><![CDATA[http://dx.doi.org/10.1023/B:IJPP.0000023480.82632.87 ]]></url>
              <type><![CDATA[DOI]]></type>
              <source><![CDATA[]]></source>
            </link>
                  </fulltext>
      </media>
      <review_dateofpub>08-SEP-04</review_dateofpub>
      <computingreviews_number>0502-0223</computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[Research papers can generally be assigned to one of two broad categories: surveys or achievements. Surveys describe progress in a specific research field as a whole. Achievement papers describe a single, incremental advance, obtained by one team in one set of experiments. This paper is both. The authors describe an incremental advance in distributed shared memory (DSM), but they cite so many other]]></review_text>
      <review_link><![CDATA[http://www.reviews.com/review/review_review.cfm?review_id=130094]]></review_link>
      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="122111">
            <reviewer_name><![CDATA[Bayard Kohlhepp]]></reviewer_name>
            <reviewer_institution><![CDATA[BayardK.com]]></reviewer_institution>
            <reviewer_location><![CDATA[Mars Hill]]></reviewer_location>
            <reviewer_country><![CDATA[United States]]></reviewer_country>
            <reviewer_url><![CDATA[http://www.bayardk.com]]></reviewer_url>
            <review_count>49</review_count>
            <displayorder>1</displayorder>
          </reviewer>
              </reviewers>
    </review>
      <review id="133258">
      <media id="1774310">
                                                        <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="1219">
                <term>General</term>
                <categorycode>G.1.0</categorycode>
              </ccs>
                          <ccs id="2455">
                <term>Model Development</term>
                <categorycode>I.6.5</categorycode>
              </ccs>
                          <ccs id="1224">
                <term>Parallel Algorithms</term>
                <categorycode>G.1.0</categorycode>
              </ccs>
                          <ccs id="3060">
                <term>Stochastic Processes</term>
                <categorycode>G.3</categorycode>
              </ccs>
                              </ccs_terms>
        <media_citation>
          <citation_details><authors><author id="2494302"><firstname><![CDATA[Debora R.]]></firstname><lastname><![CDATA[Roberti]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>1</displayorder></author><author id="2440565"><firstname><![CDATA[Roberto P.]]></firstname><lastname><![CDATA[Souto]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>2</displayorder></author><author id="2234161"><firstname><![CDATA[Haroldo F.]]></firstname><lastname><![CDATA[de Campos Velho]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>3</displayorder></author><author id="2494303"><firstname><![CDATA[Gervasio A.]]></firstname><lastname><![CDATA[Degrazia]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>4</displayorder></author><author id="2494304"><firstname><![CDATA[Domenico]]></firstname><lastname><![CDATA[Anfossi]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>5</displayorder></author></authors><citation type="Article"><title><![CDATA[Parallel implementation of a Lagrangian stochastic model for pollutant dispersion]]></title><subtitle><![CDATA[]]></subtitle><published>2005-10-01 00:00:00.0</published><start_page>485</start_page><end_page>498</end_page><sponsoredby><![CDATA[5]]></sponsoredby><issueseries><![CDATA[]]></issueseries><volume>33</volume><start_date>2005-10-01 00:00:00.0</start_date><end_date>2005-10-01 00:00:00.0</end_date><journal_title><![CDATA[International Journal of Parallel Programming]]></journal_title><journal_start_date>1989-02-01 00:00:00.0</journal_start_date><journal_end_date></journal_end_date><journal_id>5788</journal_id></citation></citation_details>        </media_citation>
        <fulltext>
                      <link>
              <url><![CDATA[http://dx.doi.org/10.1007/s10766-005-7302-z]]></url>
              <type><![CDATA[DOI]]></type>
              <source><![CDATA[ACM]]></source>
            </link>
                  </fulltext>
      </media>
      <review_dateofpub>05-SEP-06</review_dateofpub>
      <computingreviews_number>0707-0700</computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[The modeling of pollutant dispersion is very important for various applications, the most important of which is urban planning. Numerical modeling of pollutant dispersion is complicated by the fact that it is governed by turbulence in the atmospheric boundary layer. One of the implications of this is that the problem becomes computationally intensive. The authors of this paper were motivated to]]></review_text>
      <review_link><![CDATA[http://www.reviews.com/review/review_review.cfm?review_id=133258]]></review_link>
      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="123042">
            <reviewer_name><![CDATA[Anupam  Sharma]]></reviewer_name>
            <reviewer_institution><![CDATA[General Electric Global Research Center]]></reviewer_institution>
            <reviewer_location><![CDATA[Niskayuna]]></reviewer_location>
            <reviewer_country><![CDATA[United States]]></reviewer_country>
            <reviewer_url><![CDATA[]]></reviewer_url>
            <review_count>3</review_count>
            <displayorder>1</displayorder>
          </reviewer>
              </reviewers>
    </review>
      <review id="134511">
      <media id="1779231">
                                                        <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="931">
                <term>Processors</term>
                <categorycode>D.3.4</categorycode>
              </ccs>
                          <ccs id="2996">
                <term>Reusable Libraries</term>
                <categorycode>D.2.13</categorycode>
              </ccs>
                          <ccs id="2993">
                <term>Reusable Software</term>
                <categorycode>D.2.13</categorycode>
              </ccs>
                          <ccs id="532">
                <term>Software Libraries</term>
                <categorycode>D.2.2</categorycode>
              </ccs>
                          <ccs id="550">
                <term>Software/Program Verification</term>
                <categorycode>D.2.4</categorycode>
              </ccs>
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            <review_text><![CDATA[It isn&#8217;t clear how this paper relates to the journal in which it appears. Parallel programming does not appear in this 20-page paper before page 16, where it is discussed for a little over a page. Moreover, the abstract does not even mention it. Thus, it is not easy to understand the purpose of this paper.

A short section about genericity in programming languages introduces the term]]></review_text>
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            <review_text><![CDATA[Grid computing is an evolving computing paradigm leveraging potentially underutilized computing resources across a wide area network, resulting in a higher performance, large-scale virtual distributed computing system. This paper addresses the challenging dynamic resource scheduling issues of large grid collaborative applications through the introduction of a grid workflow programming model encapsulated]]></review_text>
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      <review_dateofpub>14-SEP-06</review_dateofpub>
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            <review_text><![CDATA[It&amp;#8217;s difficult to understand why programs in modern languages, running on today&amp;#8217;s complex architectures, perform the way they do. A popular approach to this problem is to use sophisticated simulators to obtain detailed traces of program execution, and then explain performance in terms of patterns of resource use. If that approach is to be widely used, compiler/simulator pairs]]></review_text>
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      <review_dateofpub>16-OCT-07</review_dateofpub>
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            <review_text><![CDATA[Pervasive computing poses a dilemma: ever-increasing amounts of data must be generated and integrated increasingly quickly, but the work must be performed by smaller computers dispersed over greater computational distances. Parallel computing with Java mobile agents (PaCMAn) is a distributed metacomputer framework built on mobile Java agents that attempts to solve this dilemma.



The twin]]></review_text>
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            <reviewer_name><![CDATA[Bayard Kohlhepp]]></reviewer_name>
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      <review_dateofpub>13-DEC-06</review_dateofpub>
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            <review_text><![CDATA[In this paper, an implementation of data-driven multithreading is proposed and evaluated. The authors investigate the speedup and power savings of a chip multiprocessor customized to include a data-driven scheduler component.

Preliminary modeling and simulation are used to compare the proposed architecture to commercially available processors. The goal is to achieve either better performance]]></review_text>
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            <review_text><![CDATA[The research presented in this paper is important and fruitful. However, it is not very accessible due to its length (56 pages) and presentation.

As the increasing complexity of hardware architectures moves them away from the usual programming languages, the importance of the optimizing parts of compilers grows. In order to achieve only a fraction of the peak performance theoretically]]></review_text>
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            <review_text><![CDATA[Amdahl&#8217;s law is about the overall system speedup when performance improvements affect only some fraction of that system. In this paper, Paul and Meyer argue that this law is incomplete: it does not take into consideration the possibility of performance losses to other system components. That is, the modifications done to the system to improve the performance of some components could harm performance]]></review_text>
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                                                        <media_issn>08857458</media_issn>
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                                    <ccs id="257">
                <term>Multiple Data Stream Architectures (Multiprocessors)</term>
                <categorycode>C.1.2</categorycode>
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                          <ccs id="386">
                <term>Performance Attributes</term>
                <categorycode>C.4</categorycode>
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          <citation_details><authors><author id="2156529"><firstname><![CDATA[JoAnn M.]]></firstname><lastname><![CDATA[Paul]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>1</displayorder></author><author id="2509078"><firstname><![CDATA[Brett H.]]></firstname><lastname><![CDATA[Meyer]]></lastname><type><![CDATA[AUTHOR]]></type><displayorder>2</displayorder></author></authors><citation type="Article"><title><![CDATA[Amdahl&#8217;s law revisited for single chip systems]]></title><subtitle><![CDATA[]]></subtitle><published>2007-04-01 00:00:00.0</published><start_page>101</start_page><end_page>123</end_page><sponsoredby><![CDATA[2]]></sponsoredby><issueseries><![CDATA[]]></issueseries><volume>35</volume><start_date>2007-04-01 00:00:00.0</start_date><end_date>2007-04-01 00:00:00.0</end_date><journal_title><![CDATA[International Journal of Parallel Programming]]></journal_title><journal_start_date>1989-02-01 00:00:00.0</journal_start_date><journal_end_date></journal_end_date><journal_id>5788</journal_id></citation></citation_details>        </media_citation>
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                      <link>
              <url><![CDATA[http://dx.doi.org/10.1007/s10766-006-0028-8]]></url>
              <type><![CDATA[DOI]]></type>
              <source><![CDATA[ACM]]></source>
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      <review_dateofpub>03-MAR-08</review_dateofpub>
      <computingreviews_number>0901-0058</computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[Paul and Meyer reexamine the implications of Amdahl&#8217;s law on single-chip heterogeneous multiprocessor (SCHM) designs. Amdahl&#8217;s law does not consider the properties of heterogeneity and finiteness that are present in SCHMs. SCHMs usually run applications with task-level heterogeneous concurrency; therefore, design strategies make the assumption that performance may be improved in isolation,]]></review_text>
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      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="122876">
            <reviewer_name><![CDATA[Carlos Juiz]]></reviewer_name>
            <reviewer_institution><![CDATA[Universitat de les Illes Balears]]></reviewer_institution>
            <reviewer_location><![CDATA[Palma de Mallorca]]></reviewer_location>
            <reviewer_country><![CDATA[Spain]]></reviewer_country>
            <reviewer_url><![CDATA[http://dmi.uib.es/~cjuiz/]]></reviewer_url>
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    </review>
      <review id="135497">
      <media id="1960191">
                                                        <media_issn>08857458</media_issn>
                          <ccs_terms>
                                    <ccs id="225">
                <term>General</term>
                <categorycode>C.0</categorycode>
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                          <ccs id="381">
                <term>Performance Of Systems</term>
                <categorycode>C.4</categorycode>
              </ccs>
                          <ccs id="400">
                <term>Super (Very Large) Computers</term>
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                      <link>
              <url><![CDATA[http://dx.doi.org/10.1007/s10766-007-0037-2]]></url>
              <type><![CDATA[DOI]]></type>
              <source><![CDATA[ACM]]></source>
            </link>
                  </fulltext>
      </media>
      <review_dateofpub>22-APR-08</review_dateofpub>
      <computingreviews_number>0902-0162</computingreviews_number>
      <status>Printed</status>
            <review_text><![CDATA[The IBM Blue Gene/L supercomputer at the Lawrence Livermore National Laboratory was ranked first on the TOP500 Web site in November 2005. In this paper, authored by more than 40 IBM staff members, the architecture, rollout, and accomplishments of the Blue Gene/L are presented in an easy-to-read form.
This machine uses 32-bit PowerPC central processing units (CPUs), with a special lightweight]]></review_text>
      <review_link><![CDATA[http://www.reviews.com/review/review_review.cfm?review_id=135497]]></review_link>
      <copyright>Copyright Reviews.com</copyright>
      <reviewers>
                  <reviewer id="107740">
            <reviewer_name><![CDATA[G. K. Jenkins]]></reviewer_name>
            <reviewer_institution><![CDATA[Victorian Partnership for Advanced Computing]]></reviewer_institution>
            <reviewer_location><![CDATA[Melbourne]]></reviewer_location>
            <reviewer_country><![CDATA[Australia]]></reviewer_country>
            <reviewer_url><![CDATA[]]></reviewer_url>
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